1. Field of the Invention
The present invention relates to substrate bias generating circuitry for maintaining a substrate loaded with a semiconductor integrated circuit (IC) or similar IC at a predetermined potential.
2. Description of the Prior Art
It has been customary with a memory or similar semiconductor IC to provide a semiconductor substrate with a substrate bias generating circuit for the purpose of preventing the substrate from reaching a given potential (e.g. positive potential) and thereby being biased in the forward direction, or for the purpose of reducing the coupling capacitance to promote rapid response. Specifically, a substrate bias voltage generated by the substrate bias generating circuit (usually a negative voltage) is applied across the semiconductor substrate to bias it in the reverse direction.
Substrate bias generating circuitry for the above application has been proposed in various forms, as disclosed in Japanese Patent Laid-Open Publication Nos. 121269/1982 and 190746/1987 by way of example. A circuit typical of such prior art circuitry is shown in FIG. 2 of the accompanying drawings.
In FIG. 2, the prior art substrate bias generating circuitry has an oscillator 10 for generating oscillating output pulses S10, FIG. 3, and a substrate bias level sensing circuit 20 for sensing the level of a substrate bias voltage Vbb to produce a control signal S20. A charge pump circuit 30 is connected to the outputs of the circuits 10 and 20 in order to generate the substrate bias voltage Vbb.
The substrate bias level sensing circuit 20 has a series connection of n-channel MOS transistors 21, 22 and 23 between a power source voltage Vcc and the substrate bias voltage Vbb. Inverters 24 and 25 are connected in series to a node N1 between the MOS transistors 21 and 22. The charge pump circuit 30 has a NAND gate 31 which is connected to the outputs of the oscillator 10 and substrate bias level sensing circuit 20. A node N3 is connected to the output node N2 via a capacitor 32. The node N3 is connected to ground potential Vss via an n-channel MOS transistor 33 and to the substrate 1 via an n-channel MOS transistor 34 and a node N4.
The operation of the prior art circuitry shown in FIG. 2 will be described with reference to FIG. 3. As shown, when the control signal S20 appearing on the output of the substrate bias level sensing circuit 20 is in (logical) high level or "H", the charge pump circuit 30 performs a pumping operation in response to an output pulse S10 of the oscillator 10. More specifically, when the output pulse S10 is in (logical) low level or "L" and the node N2 is in "H", the potential on the node N3 is equal to a threshold voltage Vt of the n-channel MOS transistor 33 and, hence, both the n-channel MOS transistors 33 and 34 remain turned off. On the turn of the output pulse S10 from "L" to "H", the node N2 turns from "H" to "L" so that the potential on the node N3 is lowered to (Vt-Vcc) by the capacitor 32. Consequently, the n-channel MOS transistor 34 is turned on to in turn cause the node N4 to output the substrate bais voltage Vbb and feed it to the substrate 1. Afterwards, the potential on the node N3 is restored to Vbb-Vt, and the MOS transisitor 34 is rendered non-conductive.
As the level of the substrate bias voltage Vbb lowers, the level on the node N1 also lowers in response thereto. Upon the level on the node N1 going lower than circuit threshold level V0 of inverter 24, the control signal S20 turns from "H" to "L". On the change of the control signal S20 to "L", the node N2 turns from "L" to "H". Upon the transition of the potential of the node N2 to "H", the capacitor 32 causes the potential on the node N3 to be elevated to (Vbb-Vt+Vcc).
Afterwards, as soon as the substrate bias voltage Vbb rises, the level on the node N1 goes also high in response thereto. Upon the level on the node N1 rising beyond circuit threshold level V0, the control signal S20 turns to "H" to cause the charge pump circuit 30 to perform a pumping operation, as previously stated.
The prior art circuitry described above with reference to FIG. 2 has some critical problems left unsolved. Specifically, assume that the potential on the node N1 has fluctuated up or down around the circuit threshold of the inverter 24, i.e., the reference level V, due to the change in any of the voltages Vcc, Vss and Vbb. Then, the duration for the control signal to remain in "H" varies and thereby prevents the control signal from remaining in "H" even for the minimum period of time necessary for the pumping operation of the charge pump circuit 30. In this condition, the potential on the node N3 fails to reach a sufficiently high level, rendering the pumping operation inaccurate and unstable. This would lead to a decrease in the efficiency of substrate bias voltage Vbb supply.